A typical circuit board module includes a printed circuit board and a variety of circuit board components soldered to the printed circuit board. Examples of circuit board components include, among other things, (i) complex integrated circuit (IC) devices such as processors, memories, Application Specific Integrated Circuits (ASICs) and (ii) discrete components such as individual resistors, individual capacitors, and the like.
As complex IC device technologies evolve, such devices have tended to use faster signal edges and higher clock rates, and have become more sensitive due to reduced noise margins. As a result, circuit board manufacturers have followed a variety of conventional approaches to providing cleaner power supply signals (i.e., a ground reference, a positive DC voltage signal, etc.) to these complex IC devices.
One conventional approach to providing improved power supply signals (hereinafter referred to as the conventional lengthwise decoupling capacitor approach) involves the manufacturer installing power signal decoupling capacitors lengthwise within cross-patterns on the undersides of printed circuit boards. That is, for high density Area Array Package (AAP) devices such as Ball Grid Array (BGA) devices and Ceramic Column Grid Array Package (CCGA) devices, printed circuit boards typically have an array of cut-through vias (i.e., plated through holes) which connect traces within the printed circuit board (e.g., data lines, power planes, ground planes, etc.) to surface mount pads that solder to the AAP devices. Manufacturers typically offset these cut-through vias to leave a horizontal gap and a vertical gap (i.e., a cross-pattern) through the via array. Then, on the undersides opposite the mounting locations for the AAP devices, the manufacturers solder decoupling capacitors lengthwise within these horizontal and vertical gaps, i.e., with the long axes of the decoupling capacitors extending along the axes of the horizontal and vertical gaps. Accordingly, the decoupling capacitors are positioned in effective locations close to the vias and alleviate the need to consume additional circuit board space around the AAP devices. During operation, these decoupling capacitors reduce noise components within the power supply signals provided to the AAP devices (e.g., low to mid-frequency filtering) thus improving reliability of the complex IC devices.
Another conventional approach to providing improved power supply signals to complex IC device (hereinafter referred to as the conventional interleaved patterning approach) involves the manufacturers interleaving power supply signals through the cut-through vias. For example, suppose that several cut-through vias are configured to carry a positive DC voltage. The manufacturers attempt to configure the vias adjacent to these “power” cut-through vias so that they carry ground references. Similarly, for cut-through vias configured to carry the ground reference, the manufacturers attempt to configure the vias adjacent to these “ground” cut-through vias to carry positive DC voltage signals. Such interleaving of power and ground signals tends to minimize total loop inductance (i.e., capacitor mounting inductance and package loop inductance which are limiting factors on decoupling capacitor efficiency) and thus provides improved power signal conditioning.